Supply voltage tolerant phase-locked loop circuit

ABSTRACT

A phase-locked loop design is provide that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.

TECHNICAL FIELD

The present invention relates to integrated circuit devices, and moreparticularly to a phase-locked loop integrated circuit.

BACKGROUND OF THE INVENTION

Until recently, most of the integrated circuits were designed to operatewith a single 5 V power supply voltage. But with the advent of portablePCs and energy efficient "green" PCs, many integrated circuits now haveto be able to operate at both 3.3 V and 5 V. It is usually not a problemfor digital circuits as long as the circuits can operate at the requiredclock frequency at 3.3 V. But for analog circuits, operating at adifferent supply voltage can be a complicated issue, especially for theanalog phase-locked loops (PLL). For example, the frequency range of aPLL usually has a strong dependency on the power supply voltage. FIG. 1shows a typical PLL circuit known in the art. As shown in FIG. 2A-2B, aPLL designed for 3.3 V operation can be too fast for 5 V operation,especially if variations in temperature and process conditions are alsotaken into account. Similarly, a PLL designed to operate at 5 V can betoo slow if operated at 3.3 V.

It is an object of the present invention to provide a method foradjusting the frequency range of a PLL based on supply voltage so thatthe same PLL design can operate at different supply voltages.

It is yet another object of the present invention to provide PLL thatcan operate at both 3.3 V and 5 V.

SUMMARY OF THE INVENTION

A phase-locked loop design is provided that can operate at a pluralityof dissimilar supply voltages. By adjusting the frequency range of a PLLbased on the power supply voltage, the same PLL design can operate atdifferent supply voltages.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows a traditional phase-locked loop circuit

FIGS. 2A and 2B graphically depicts problems encountered when PLL supplyvoltage changes.

FIG. 3 is a block diagram of an improved phase-locked loop.

FIG. 4 is a schematic of a supply voltage detector circuit.

FIG. 5 is a detailed block diagram of an improved phase-locked loop.

FIG. 6 is a schematic for changing the reference voltage/current of aPLL using a voltage to current converter.

FIG. 7 is a schematic for changing the reference voltage/current of aPLL using a voltage to current converter, and including supply voltagedetection circuitry.

FIG. 8 is a schematic for changing the reference voltage/current of aPLL using a linear current source, and including supply voltagedetection circuitry.

FIG. 9 is a schematic for changing the reference voltage/current of aPLL using a linear current source.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 3 shows how to adjust the frequency range of a PLL based on supplyvoltage. First, the power supply voltage level is detected by detector12. The detector output 13 is coupled to the PLL 14. Supply voltagedetector 12 operates by comparing the supply voltage VDD with areference voltage VREF which is independent of the supply voltage. Thereference voltage VREF can come from an external voltage regulator or begenerated on-chip by a bandgap reference voltage source. Since thereference voltage VREF will generally be lower than the supply voltageVDD, the reference voltage cannot be compared directly with the supplyvoltage. Rather, the supply voltage is scaled and compared with thereference voltage. There are many possible ways to scale down the supplyvoltage. One way is to use a voltage divider as shown in FIG. 4. If allthat is needed is to operate the PLL at 3.3 V and 5 V, a divide-by-twovoltage divider R1/R2 is used to scale the supply voltage VDD from 3.3 Vto 1.65 V and from 5 V to 2.5 V. For an equal margin on both sides, a2.075 V reference voltage VREF is used to detect the supply voltage.

Once the supply voltage level is detected, the next step is to find away to adjust the PLL frequency range accordingly. A possible solutionis to insert a frequency divider which can be enabled when operated at 5V to divide down the PLL output frequency. FIG. 5 shows a phase-lockedloop 14 comprising a phase detector 18, charge pump 20, low pass filter22 and VCO/ICO 24. However, as also shown in FIG. 5, the PLL has beenmodified to include a frequency divider 26 between the VCO/ICO 24 andthe phase detector 18. The output 27 from the frequency divider 26 isselected by the multiplexer 28 if a 5 V supply voltage is detected, asindicated by control line 13 (which may be generated by the circuitshown in FIG. 4).

However, there are a few drawbacks associated with this approach. Firstof all, the frequency divider 26 requires extra silicon area andconsumes extra power at relatively high frequency. Secondly, if anon-integer divider is required, it could be difficult to implement. Aneasier way to adjust the PLL frequency range is to adjust the referencevoltage or current 40 that goes into the PLL. Most of the VCO(Voltage-Controlled Oscillator) or ICO (Current-Controlled Oscillator)based PLLs have either an external voltage or current source thatdetermines the PLL's center operating frequency, one such oscillatorbeing described in U.S. Pat. No. 5,302,920 entitled "ControllableMulti-Phase Ring Oscillators with Variable Current Sources andCapacitances", which is hereby incorporated by reference. By changingthe reference voltage or current 40, the PLL frequency range can beadjusted based on the detected supply voltage.

FIG. 6 gives an example on how this can be done by adding twotransistors M1 and M2, which function as a voltage to current (V-I)converter 34. The reference current going into the PLL at 40, which isthe sum of current source output 36 and V-I converter output 38, isreduced by turning off the transistor M1 when a 5V power supply voltageis detected, as indicated by control line 13. If a 3.3 V power supplyvoltage is detected, transistor M1 is turned on, and supplies additionalcurrent to the PLL via output 38 to PLL input 40.

FIG. 7 shows how to operate the PLL at both 3.3 V and 5 V. It is evenbetter if the frequency range could be adjusted linearly with the supplyvoltage so that the PLL could operate at any supply voltage level. Thisis done by replacing the comparator 16 of FIG. 4 with a differentialamplifier, as shown at 30 in FIG. 8. The output 52 of the differentialamplifier is proportional to the difference between thesupply-independent reference voltage VREF and the scaled supply voltageVDD. This output voltage 52 is then used to adjust the referencevoltage/current going into the PLL, similar to the technique that waspreviously described with respect to FIG. 6. However, since thedifferential amplifier provides an analog output voltage (as opposed toa digital output from the comparator of FIG. 7), a simplified voltage tocurrent converter 44 is used.

As shown in FIG. 9, the simplified voltage to current converter onlyrequires a single transistor M3, which is biased by the output voltage52 from the differential amplifier 30.

The circuit of FIG. 8 thus provides a technique for adjusting thereference current linearly with the supply voltage, such that the PLLcan operate at a plurality of dissimilar supply voltages.

While I have illustrated and described the preferred embodiments of ourinvention, it is to be understood that I do not limit myself to theprecise constructions herein disclosed, and the right is reserved to allchanges and modifications coming within the scope of the invention asdefined in the appended claims.

I claim: .[.
 1. A method for operating a phase-locked loop, comprisingthe steps of:detecting a supply voltage; and adjusting the operatingfrequency of the phase-locked loop based upon the detected supplyvoltage..].
 2. A method to adjust the frequency range of a phase-lockedloop, comprising the steps of:detecting a supply voltage; and enablingor disabling one or more frequency dividers in the PLL based upon thedetected supply voltage. .[.3. A method to adjust the frequency range ofa phase-locked loop (PLL), comprising the steps of: detecting a supplyvoltage; and adjusting a PLL reference voltage or current based upon thedetected supply voltage..]..[.4. A phase-locked loop, comprising: meansfor detecting a supply voltage; and means for adjusting the operatingfrequency of the phase-locked loop based upon the detected supplyvoltage..].5. A system for adjusting the frequency range of aphase-locked loop, comprising:means for detecting a supply voltage; andmeans for selectively enabling at least one frequency divider in the PLLbased upon the detected supply voltage. .[.6. A system for adjusting thefrequency range of a phase-locked loop (PLL), comprising:means fordetecting a supply voltage; and means for adjusting a PLL referencevoltage or current based upon the detected supply voltage..]..[.7. Aphase-locked loop circuit powered by a supply voltage, comprising: atleast one current source which adjusts the reference operating point ofan oscillator in said phase-locked loop based upon the supplyvoltage..]..[.8. A phase-locked loop circuit powered by a supplyvoltage, comprising: a phase detector operatively coupled to a chargepump; a filter operatively coupled to the charge pump; an oscillator,operatively coupled to the filter, said oscillator having a referenceoperating point; and adjusting means for dynamically adjusting thereference operating point based upon the supply voltage..]..[.9. Thecircuit of claim 8 wherein the adjusting means comprises a plurality ofcurrent sources..]..[.10. The circuit of claim 9 further comprisingmeans for selectively enabling at least one of the plurality of currentsources..].11. A circuit for adjusting the .[.reference operatingpoint.]. .Iadd.frequency range .Iaddend.of a phase-locked loop,comprising:a differential amplifier having a reference voltage input anda scaled supply voltage input.Iadd., said differential amplifiergenerating an output that is proportional to a difference between saidreference voltage input and said scaled supply voltage input.Iaddend.; alinear current source having at least one input coupled to .[.an.]..Iadd.said .Iaddend.output of .[.the.]. .Iadd.said .Iaddend.differentialamplifier.Iadd., said linear current source providing a current outputrelated to said output of said differential amplifier.Iaddend.; and afixed current source coupled to an output of the linear currentsource.Iadd., said fixed current source generating an output and,together with said current output of said linear current source, beingused to adjust a signal applied to the phase-locked loop.Iaddend...[.12. A phase-locked loop circuit powered by a supply voltage,comprising: a phase detector operatively coupled to a charge pump; afilter operatively coupled to the charge pump; an oscillator,operatively coupled to the filter, said oscillator having a referenceoperating point; and at least one current source which adjusts thereference operating point of said oscillator based upon the supplyvoltage..]..Iadd.13. A circuit of claim 11 wherein said scaled supplyvoltage input is provided using a supply voltage and said referencevoltage input is provided independently of said supply voltage..Iaddend.